1. Field of the Invention
This invention relates to computer systems, and more particularly, to methods and apparatus for programming flash EEPROM memory cells which store a plurality of bits of data.
2. History of the Prior Art
Recently, flash electrically-erasable programmable read only memory (flash EEPROM memory) has been used as a new form of long term storage. A flash EEPROM memory array is constructed of floating gate field effect transistor devices. Such memory transistors may be programmed by storing a charge on the floating gate. The charge level (programmed or erased) may be detected by interrogating the cells. An example of a flash EEPROM memory array which may be used in place of a hard disk drive is given in U.S. patent application Ser. No. 07/969,131, entitled A Method and Circuitry For A Solid State Memory Disk, S. Wells, filed Oct. 31, 1992, and assigned to the assignee of the present invention. These arrays provide a smaller lighter functional equivalent of a hard disk drive which operates more rapidly and is not as sensitive to physical damage. Such memory arrays are especially useful in portable computers where space is at a premium and weight is extremely important.
Recently, it has been discovered that the transistor devices used for flash EEPROM memory arrays may be made to store more than two charge levels. Essentially, four or more distinct levels of charge may be stored on the floating gate of the devices by varying the voltages applied to the terminals of the devices during programming; and these different charge levels (conditions or states) may be detected. This allows flash EEPROM devices in memory arrays to store more than one bit per device and radically increases the storage capacity of such arrays.
Flash EEPROM memory arrays, like other transistor memory arrays utilize reference devices to store values against which the memory cells are tested to determine their charge level when the memory cells are read. These reference devices are typically flash EEPROM devices similar to those used for storing data in the array. In a typical prior art memory array in which two possible charge levels are available for each memory cell, the reference devices are programmed to a charge level to produce a particular current value when interrogated which is midway between the two charge levels in which the memory cells may be placed. The current through the reference device in turn produces a voltage which is measured against a voltage produced by current through a memory cell.
With the new storage arrangements in which more than one bit may be stored by each memory transistor, many more reference cells are utilized since many more levels must be tested to determine a value stored by the floating gate of a memory cell. Since a number of voltage levels must be measured, the values stored by the reference cells need to be very accurately determined.
A number of problems arise in utilizing these multiple bit memory cells because of the more restricted range of charges which provide each output state. For example, in order to program the cells, an algorithm is utilized which provides a first high level of voltage to the gate terminals of a number of the memory transistors being programmed for a prescribed interval. This initial voltage pulse moves the memory transistors into their saturation range of operation in which they may be controlled more closely. The initial pulse is followed by shorter pulses of incrementally higher voltage which gradually increase the charges on the floating gates and move the devices to the appropriate charge levels. After each of these pulses, the condition of each memory cell being programmed is verified.
Once at a desired charge level, some charge leakage may occur. It is possible for a device to have reached a proper state, lose some charge, and when later tested fail to verify as being in the proper state even though the device is still within an appropriate charge range for correct operation. Since the charging algorithm would apply a voltage which had been incremented to a relatively high level to the gate of any device which did not verify, it should not be utilized with a device in a state just slightly below the verify charge level.
A second problem is caused because of the physical differences in memory devices. Statistically, some devices differ from others. They may have longer or wider channels or other characteristics which differ. Because of this, some devices charge rapidly while others charge slowly. If a device which charges rapidly is being charged to the highest charge level, it may charge to a condition at which the device may be damaged through the repeated charging and discharging inherent in programing and erasing. Consequently, it is necessary to eliminate this overcharging problem so that the faster charging devices and thus the memory array will not fail rapidly in use.
A third problem is caused by the software method by which the verify operations have been accomplished in the prior art; these have been relatively time consuming operations when even a single bit is to be stored for each memory cell. The verify operation becomes very complicated and quite slow when applied to multi-level memory cells. Consequently, an improved method of verifying the programming of multi-level memory cells is desirable.